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MSM5718C50 - (MSM5718C50 / MSM5764802) 18Mb (2M x 9) & 64Mb (8M x 8) Concurrent RDRAM

Description

The 18/64-Megabit Concurrent Rambus™ DRAMs (RDRAM®) are extremely high-speed CMOS DRAMs organized as 2M or 8M words by 8 or 9 bits.

They are capable of bursting unlimited lengths of data at 1.67 ns per byte (13.3 ns per eight bytes).

Features

  • Compatible with Base RDRAMs.
  • 600 MB/s peak transfer rate per RDRAM.
  • Rambus Signaling Level (RSL) interface.
  • Synchronous, concurrent protocol for block-oriented, interleaved (overlapped) transfers.
  • 480 MB/s effective bandwidth for random 32 byte transfers from one RDRAM.
  • 13 active signals require just 32 total pins on the controller interface (including power).
  • 3.3 V operation.
  • Additional/multiple Rambus Channels each provid.

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Datasheet Details

Part number MSM5718C50
Manufacturer OKI Electric
File Size 549.62 KB
Description (MSM5718C50 / MSM5764802) 18Mb (2M x 9) & 64Mb (8M x 8) Concurrent RDRAM
Datasheet download datasheet MSM5718C50 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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E2G1059-39-21 ¡ Semiconductor MSM5718C50/MD5764802 ¡ Semiconductor 18Mb (2M ¥ 9) & 64Mb (8M ¥ 8) Concurrent RDRAM This version: Feb. 1999 MSM5718C50/MD5764802 Previous version: Nov. 1998 DESCRIPTION The 18/64-Megabit Concurrent Rambus™ DRAMs (RDRAM®) are extremely high-speed CMOS DRAMs organized as 2M or 8M words by 8 or 9 bits. They are capable of bursting unlimited lengths of data at 1.67 ns per byte (13.3 ns per eight bytes). The use of Rambus Signaling Level (RSL) technology permits 600 MHz transfer rates while using conventional system and board design methodologies. Low effective latency is attained by operating the two or four 2KB sense amplifiers as high speed caches, and by using random access mode (page mode) to facilitate large block transfers.
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